In this paper a new Phase-frequency Detector is proposed using transmission gates which can detect Phase difference less than 500ps. In other word, the proposed Phase-frequency Detector (PFD) can work in frequencies higher than 1. 7 GHz, whereas a conventional PFD operates at frequencies less than 1. 1 GHz. This new architecture is designed in TSMC 0. 13um CMOS Technology. Also, the proposed PFD achieves a capture range approximately twice that of conventional PFDs. The simulation results support the theoretical predictions. To validate correct performance of this novel PFD, it is then used in a conventional delay locked loop structure.

The electronic industry has grown vastly in recent years, and researchers are trying to minimize circuits delay, occupied area and power consumption as much as possible. In this regard, many technologies have been introduced. Quantum Cellular Automata (QCA) is one of the schemes to design nano-scale digital electronic circuits. This technology has high speed and low power consumption, and occupies very little area. Phase-locked loops (PLLs) and delay-locked loops (DLLs) are blocks that are commonly used in telecommunication applications. One of the most important parts in DLL and PLL is the Phase-frequency Detector. Therefore, the design of this circuit in QCA technology is of great importance. In this paper, two new Phase-frequency Detectors sensitive to falling and rising edge have been introduced in QCA technology. Both of the designs are composed of 104 cells; occupy only 0. 13 μ m2 of an area and 1. 5 QCA clock cycles latency. The designs are in one layer and all the inputs and outputs are available to be used by another circuit.

Achieving low power consumption and low delay are the most important goals that efforts have been made to reach. In this paper, the process of designing and optimizing the Phase frequency Detector (PFD) performance at the integrated circuits (IC) level has been proposed using carbon nanotubes. In the proposed method, by using carbon nanotube transistors, improvements have been made in the output parameters of the Phase Detector. Failure to use flip-flops and the simple circuit structure will significantly increase speed and reduce power consumption. Post-layout simulation for 180nm CMOS technology and simulation results for 32nm Carbon Nanotube Field-Effect Transistor (CNTFET) technology is presented. The proposed CMOS 28T Phase Detector circuit, by injecting 30mV peak-to-peak power supply noise has 5× better operating frequency of the conventional circuit, and it has a 10% improvement in power consumption of the conventional one. Also, with carbon nanotubes, the frequency has increased 4 times, and the power consumption has improved significantly. In this case, the power consumption is 1.76 microwatts, and the operating frequency is 20 GHz. Open-loop design and elimination of the reset path, and attention to delays to remove the dead zone are the proposed circuit's top features compared with the traditional design methods.

We have developed the effective algorithm for detecting digital binary Phase-shift keyed signals. This algorithm requires a small number of arithmetic operations over the signal period. It can be relat ively easy implemented based on the modern programmable logic devices. It also provides high interference immunity by identifying signal presence when signal-to-noise ratio is much less that its working value in the receiving path. The introduced Detector has int rinsic frequency selectivity and allows us to form the est imate of the noise level to realize the adaptive determination of decision threshold. In order to get confirmation of the Detector operability and performance, we suggest the expressions for false alarm and missing probabilities. In addit ion, we have examine, both theoretically and experimentally, the influence of the Detector parameters on its characterist ics.

This work introduces a new structure of Zero Crossing Digital Phase Locked Loop with Arc Sine block (ASZCDPLL) to linearize the Phase difference detection, and enhance the loop performance. The new loop has faster acquisition, less steady state Phase error, and wider locking range as compared to the conventional ZCDPLL. The locking range improvement and faster acquisition have been confirmed through simulation. The loop has been implemented and tested in real time using Texas Instruments TMS320C6416 DSP development kit.